The present invention relates, in general, to the field of non-volatile, integrated circuit (xe2x80x9cICxe2x80x9d) memory devices and those ICs incorporating non-volatile memory arrays. More particularly, the present invention relates to a capacitance sensing technique for ferroelectric random access memory devices and arrays.
Ferroelectric memory devices, such as the FRAM(copyright) family of solid state, random access memory (xe2x80x9cRAMxe2x80x9d) integrated circuits (xe2x80x9cICsxe2x80x9d) available from Ramtron International Corporation, Colorado Springs, Colo. provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
A hysteresis curve, wherein the abscissa and ordinate represent the applied voltage and resulting polarization states respectively, may be plotted to represent the response of the polarization of a ferroelectric capacitor to the applied voltage. A more complete description of this characteristic hysteresis curve is disclosed, for example, in U.S. Pat. Nos. 4,914,627 and 4,888,733 assigned to the assignee of the present invention, the disclosures of which are herein specifically incorporated by this reference.
Data stored in a ferroelectric memory cell is xe2x80x9creadxe2x80x9d by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce either a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d at the IC output pins. In a conventional two transistor/two capacitor (xe2x80x9c2T/2Cxe2x80x9d) ferroelectric memory cell, a pair of two data storage elements are utilized, each polarized in opposite directions. To xe2x80x9creadxe2x80x9d the state of a 2T/2C memory cell, the elements are polarized in opposite directions and the sense amplifiers measure the difference between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a xe2x80x9creadxe2x80x9d to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell during a precharge operation.
In a simple xe2x80x9cwritexe2x80x9d operation, an electric field is applied to the cell capacitor to polarize it to the desired state. For a 2T/2C cell, a field in the opposite direction is used to polarize the reference capacitor.
One conventional technique for reading data from a ferroelectric memory device is shown in U.S. Pat. No. 6,285,575 issued Sep. 4, 2001 to Miwa for: xe2x80x9cShadow RAM Cell and Non-Volatile Memory Device Employing Ferroelectric Capacitor and Control Method Thereforxe2x80x9d which describes a device wherein ferroelectric capacitors are xe2x80x9cone for onexe2x80x9d coupled in with an SRAM cell and are only used when the shadow RAM device is xe2x80x9cpowered upxe2x80x9d in a six transistor (xe2x80x9c6Txe2x80x9d) shadow RAM application. See also, Miwa et al., xe2x80x9cNV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitorsxe2x80x9d, IEEE Journal of Solid-State Circuits Vol. 36, No. 3, March 2001 at pp. 522-527. A further representative description of a ferroelectric memory xe2x80x9creadxe2x80x9d operation is described in U.S. Pat. No. 5,615,144 issued Mar. 25, 1997 for: xe2x80x9cNon-Volatile Ferroelectric Memory Device with Leakage Preventing Functionxe2x80x9d. Each of these publications describes a relatively slow conventional sensing operation which does not serve to decrease xe2x80x9creadxe2x80x9d operation latency.
The capacitance sensing technique for ferroelectric random access memory devices and arrays of the present invention, as disclosed herein, advantageously enables fast sensing operations to be performed as opposed to that of conventional techniques in which only much slower sensing can be effectuated. By enabling this faster sensing, the technique disclosed herein allows for low latency xe2x80x9creadxe2x80x9d operations thereby providing overall system performance advantages.
Through the use of the technique of the present invention, concurrent polling and reading of data may be achieved prior to pulsing (or driving) the plate line. This then allows the memory xe2x80x9crestorexe2x80x9d function to be hidden behind the xe2x80x9creadxe2x80x9d data stream at the memory device output pins. In contrast, with conventional memory device operation it is the plate line driver (or pulse) that interrogates the memory, generates a voltage and then allows sensing to both restore the data and prepare the data for the outputs. As disclosed herein, the sensing may, in accordance with the present invention, begin prior to pulsing the plate line and it is the sensing process itself which interrogates the memory and concurrently prepares the data for the outputs. In this manner, it is the pulsing of the plate line after the data is sensed that performs the xe2x80x9crestorexe2x80x9d and this operation is not a portion of the xe2x80x9creadxe2x80x9d access time critical path.
Through the technique of the present invention, lower capacitance bit lines may also be employed. This is a distinct advantage over those which are employed in conventional memory devices where the bit line capacitance must be large relative to the capacitance of the ferroelectric capacitors in order that a voltage greater than the ferroelectric coercive voltage is placed across the ferroelectric capacitor during the xe2x80x9creadxe2x80x9d interrogation. In conventional devices, the process of driving the plate line prior to the sensing operation creates a capacitor divider between the ferroelectric capacitor and the bit line. These relatively heavy bit lines consume power during the xe2x80x9csensexe2x80x9d and xe2x80x9crestorexe2x80x9d operations, add to xe2x80x9creadxe2x80x9d and xe2x80x9crestorexe2x80x9d latency and reduce the signal differential into the sense amplifiers. By way of comparison, the technique of the present invention effectively grounds the plate line during the sense operation, and thus, one hundred percent of the voltage applied occurs across the ferroelectric capacitor thereby removing all prior limitations on the bit line capacitance. Consequently, significant benefits with respect to device power consumption and the latencies of the xe2x80x9creadxe2x80x9d, xe2x80x9cwritexe2x80x9d and xe2x80x9crestorexe2x80x9d operations are achieved.
Still further, the technique of the present invention allows for improved low voltage device operation. As technologies scale to ever smaller device geometries, the operating power supply voltage levels are also concomitantly reduced, often by a greater factor than the coercive voltage of the ferroelectric capacitor is reduced. When this occurs, low voltage xe2x80x9creadsxe2x80x99 of the ferroelectric device can be compromised, requiring internally generated power supplies which, in turn, add to chip size, complexity and power requirements. Inasmuch as the technique of the present invention does not divide the xe2x80x9creadxe2x80x9d voltage down, it provides an inherent advantage in low voltage operations over that of conventional devices and techniques.
Particularly disclosed herein is a sensing technique for an integrated circuit device comprising a memory array which includes a plurality of ferroelectric memory cells coupled to complementary bit lines. The technique comprises coupling the complementary bit lines together to a reference voltage level and enabling a word line coupled to at least a portion of the ferroelectric memory cells and coupling the complementary bit lines to a sense amplifier. The complementary bit lines are then uncoupled from each other and the reference voltage level and a first enable node of the sense amplifier is enabled. Data representative of the contents of selected ones of the ferroelectric memory cells is then provided at an output of the device.
Also particularly disclosed herein is an integrated circuit device comprising a memory array including a plurality of ferroelectric memory cells having a plate line and word line inputs thereto. The ferroelectric memory cells are coupled to first and second complementary bit lines and selectively couplable to first and second input nodes of a sense amplifier. The sense amplifier comprises first and second cross-coupled inverters with the input of the first inverter being coupled to the first input node and an output node of the second inverter and the input of the second inverter being coupled to the second input node and an output node of the first inverter. Optional first and second isolation transistors respectively couple the first and second complementary bit lines to the first and second input nodes in response to an isolation signal. The sense amplifier further comprises first and second enable nodes for the first and second cross-coupled inverters with the first enable node being selectively couplable to a supply voltage source through a first enable node transistor in response to a first latch enable signal and the second enable node being selectively couplable to a reference voltage level through a second enable node transistor in response to a second latch enable signal. An equilibration circuit is provided for selectively coupling the first and second input nodes together to the reference voltage level in response to an equilibration signal.
The present invention can be implemented with or without isolation transistors and depending on the precharge condition, with one or two sense amplifier enable nodes. For example, if the bit lines are precharged low, the lower enable transistor can be eliminated and the N-channel transistors in the sense amplifier inverters can be hard wired to ground. Conversely, if the bit lines are precharged high, the upper enable transistor can be eliminated. Further, the enable transistors can be local or shared among many sense amplifiers.